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A 1.8-um pitch, 47-ps jit
A 1.8-um pitch, 47-ps jitter SPAD Array in 130nm SiGe BiCMOS Process

We introduce the world’s first SPAD family design in 130 nm SiGe BiCMOS process. At 1.8um, we achieved the smallest pitch on record thanks to guard-ring sharing techniques, while keeping a relatively high fill factor of 24.2%. 4×4 SPAD arrays with two parallel selective readout circuits were designe…

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